A multiport memory is known as a semiconductor memory capable of simultaneously executing a read operation and a write operation for one memory cell. Besides, a method shorting complementary storage nodes in a memory cell at the write operation time is proposed to improve write characteristics of the multiport memory (see, for example, U.S. Pat. No. 7,113,445 B1).
In a memory cell array, elements and wirings are laid out in high density compared to peripheral circuits. Accordingly, electric characteristics of transistors in the memory cell may vary easily. It may be therefore necessary to prevent deterioration of the electric characteristics of the memory cell or deterioration of an operation margin when the transistor shorting the complementary storage nodes is disposed in the memory cell. Besides, in a write operation, data stored in a memory cell to which data is not written may be lost caused by the shorts of the complementary storage nodes when the data is written to only a part of memory cells among the memory cells coupled to a word line.